Shift the new values from memory into the shift register at the lower bits.Code for D FlipFlop with synchronous clear and preset.Īs the array types signed and std_logic_vector have the same element type you can convert between both types the following way: signal x : std_logic_vector(7 downto 0) - 8 bit for example Signal qout : std_logic_vector(7 downto 0) Signal x : std_logic - 1st stage input, the feedback Pn1,pn2,pn3,pn4 : out STD_LOGIC) - PN sequence Init : in STD_LOGIC_vector (3 downto 0) - the seed library IEEE Ĭlock : in STD_LOGIC - synchronous clock input What changes I should do to obtain different PN sequences? I am using 1010 as a initial seed but in the output all the four PN sequences are 1. I got a code for PN sequence generator using linear feedback shift register in VHDL.
